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LTC3829 3829f 3-phase, single output synchronous step-down dc/dc controller with diffamp typical a pplica t ion descrip t ion the ltc ? 3829 is a high performance 3-phase single output synchronous step-down dc/dc switching controller that drives all n- channel synchronous power mosfet stages. a constant frequency current mode architecture allows a phase-lockable frequency of up to 770khz. power loss and noise due to esr of the input capacitors are minimized by operating the three controller output stages out of phase. the LTC3829 can be confgured for 6-phase operation, has dcr temperature compensation, and output foldback current limiting. this device features a precision 0.6v reference and a power good indicator. light load effciency is optimized by using a choice of output stage shedding or burst mode operation. a dif- ferential amplifer provides true remote sensing of the output voltage at the point of load. the LTC3829 is available in both low profle 38-pin 5mm 7mm qfn and exposed pad fe packages. fea t ures a pplica t ions n optional nonlinear control for fast response n 0.75%, 0.6v reference accuracy n pwm, stage shedding? or burst mode ? operation n high effciency: up to 95% n r sense or dcr current sensing n programmable dcr temperature compensation n phase-lockable fixed frequency: 250khz to 770khz n true remote sense differential amplifer n programmable active voltage positioning (avp) n triple n-channel mosfet synchronous drive n wide v in range: 4.5v to 38v operation n v out range: 0.6v to 5v without diffamp n v out range: 0.6v to 3.3v with diffamp n clock input and output for 6-phase operation n adjustable soft-start or v out tracking n 38-pin (5mm 7mm) qfn and fe packages n notebook and palmtop computers n telecom systems n portable instruments n dc power distribution systems + + intv cc boost1 boost2 boost3 freq i th tk/ss sense1 + sense1 ? pgnd bg1 sw1 tg1 4.7f sw3 sw2 sw1 0.1f 680pf 100k 5k 20k 20k 22f 35v s3 v in 6v to 28v c out 470f 4v s4 v out 1.2v 50a sense2 + sense2 ? bg2 sw2 tg2 sense3 + sense3 ? bg3 sw3 tg3 sgnd diffout v fb diffn diffp 0.6h v in v in 0.002 0.6h 0.002 0.6h 3829 ta01 0.002 v in LTC3829 l , lt, ltc, ltm, burst mode, opti-loop, polyphase, linear technology, the linear logo are registered trademarks and stage shedding, no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 6498466, 6674274, 6611136. load current (a) 0.1 70 efficiency (%) power loss (w) 75 80 85 90 1 10 100 3829 ta01b 65 60 55 50 95 100 4 6 8 10 12 2 0 14 16 v in = 12v v out = 1.5v efficiency power loss effciency
LTC3829 3829f input supply voltage (v in ) ......................... 40v to C0.3v topside driver voltages (boostn) ............ 46v to C0.3v switch voltage (swn) ................................... 40v to C5v boosted driver voltage (boostn C swn) .... 6v to C0.3v intv cc , pgood, run, extv cc .................... 6v to C0.3v itemp, ifast, v fb pin voltages .............. intv cc to C0.3v tk/ss, freq, diffp, diffn, diffout, iset avp, i lim , mode, pllin voltages .......... intv cc to C0.3v (note 1) a bsolu t e maxi m u m r a t ings 13 14 15 16 top view 39 uhf package 38-lead (5mm s 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1diffn diffp run avp sense1 + sense1 ? sense2 + sense2 ? tk/ss freq sense3 + sense3 ? sw1 bg1 bg2 sw2 tg2 boost2 v in intv cc extv cc bg3 sw3 tg3 diffout itemp ifast mode clkout boost1 tg1 v fb i th iset i lim pgood pllin boost3 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is sgnd/pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 27 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 itemp diffout diffn diffp run avp sense1 + sense1 ? sense2 + sense2 ? tk/ss freq sense3 + sense3 ? v fb i th iset i lim pgood ifast mode clkout boost1 tg1 sw1 bg1 bg2 sw2 tg2 boost2 v in intv cc extv cc bg3 sw3 tg3 boost3 pllin 39 t jmax = 125c, ja = 25c/w exposed pad (pin 39) is sgnd/pgnd, must be soldered to pcb p in c on f igura t ion i th voltage ............................................ intv cc to C0.3v sense + n, sense C n ................................... 5.7v to C0.3v operating junction temperature range (notes 2, 3) ............................................ C45c to 125c storage temperature range ................... C65c to 125c lead temperature (soldering, 10 sec) (fe) ........... 300c
LTC3829 3829f o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3829euhf#pbf LTC3829euhf#trpbf 3829 38-lead (5mm 7mm) plastic qfn C40c to 125c LTC3829iuhf#pbf LTC3829iuhf#trpbf 3829 38-lead (5mm 7mm) plastic qfn C40c to 125c LTC3829efe#pbf LTC3829efe#trpbf LTC3829 38-lead plastic tssop C40c to 125c LTC3829ife#pbf LTC3829ife#trpbf LTC3829 38-lead plastic tssop C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in input voltage range 4.5 38 v v out output voltage range 0.6 5.0 v v fb regulated feedback voltage i th voltage = 1.2v (note 4) C40c to 85c i th voltage = 1.2v (note 4) t j = 125c l l 0.5955 0.593 0.600 0.600 0.6045 0.607 v v i fb feedback current (note 4) C15 C50 na v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop, ?i th voltage = 1.2v to 0.7v measured in servo loop, ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m transconductance amplifer g m i th = 1.2v, sink/source 5a (note 4) 2.2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v v run = 0v 4 40 60 ma a df max maximum duty factor in dropout, f osc = 500khz 93 94 % uvlo undervoltage lockout v intvcc ramping down l 3.0 3.3 3.6 v uvlo hyst uvlo hysteresis 0.6 v v ovl feedback overvoltage lockout measured at v fb l 0.64 0.66 0.68 v i sense1,2,3 + sense + pins bias current each channel, v sense1,2,3 = 3.3v, v diffp = 3.3v l 1 2 a i temp dcr tempco compensation current v itemp = 0.2v l 9 10 11 a i tk/ss soft-start charge current v tk/ss = 0v l 1.0 1.25 1.5 a v run run pin on threshold v run rising l 1.1 1.22 1.35 v run pin on hysteresis 100 mv v sense(max) maximum current sense threshold (e-grade) v fb = 0.5v, v sense1,2,3 = 3.3v i lim = 0v i lim = float i lim = intv cc l l l 25 45 68 30 50 75 35 55 82 mv mv mv maximum current sense threshold (i-grade) v fb = 0.5v, v sense1,2,3 = 3.3v i lim = 0v i lim = float i lim = intv cc l l l 23 43 66 30 50 75 37 57 84 mv mv mv the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 15v, v run = 5v, unless otherwise noted. (note 2) (note 2)
LTC3829 3829f e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 15v, v run = 5v, unless otherwise noted. (note 2) symbol parameter conditions min typ max units tg1,2,3 t r tg1,2,3 t f tg transition time rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg1,2,3 t r bg1,2,3 t f bg transition time rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in 38v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2.0 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 210 250 290 khz f high highest frequency v freq 2.4v 700 770 850 khz r plln pllin input resistance 100 k i freq frequency setting current 9 10 11 a i iset shed and burst mode program current 6.5 7.5 8.5 a clkout phase (relative to controller 1) non-shedding mode channel 2 and 3 shedding 60 180 deg deg clkhigh clock high output voltage 4 5 v clklow clock low output voltage 0 0.2 v pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 0 2 a v pg pgood trip level, either controller v fb with respect to set output voltage v fb ramping negative v fb ramping positive C12 8 C10 10 C7 13 % % differential amplifer a da gain l 0.997 1 1.003 v/v r in input resistance measured at diffp input 80 k v os input offset voltage v diffp = v diffout = 1.5v, i diffout = 100a 2.5 mv psrr power supply rejection ratio 5v < v in < 38v 100 db i cl maximum output current 3 ma v out(max) maximum output voltage intv cc = 5v, i diffout = 300a v intvcc C 1.4 v intvcc C 1.1 v gbw gain-bandwidth product (note 8) 3 mhz sr slew rate (note 8) 2 v/s
LTC3829 3829f symbol parameter conditions min typ max units nonlinear fast transit mode i fast fast transient programmable current v ifast = 400mv 9 10 11 a avp (active voltage positioning) i sink sink current of avp pin sense + = 1.2v 250 a i source source current of avp pin sense + = 1.2v 2 ma v avp -v o(max) maximum voltage drop v avp to v o sense + = 1.2v 180 mv v avp maximum avp voltage l 2.5 v on-chip driver tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 4 bg r down bg pull-down r ds(on) bg low 1.1 e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 15v, v run = 5v, unless otherwise noted. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3829e is guaranteed to meet performance specifcations from 0c to 85c operating junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3829i is guaranteed to meet performance specifcations over the full C40c to 125c operating junction temperature range. note 3: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: LTC3829uhf: t j = t a + (p d ? 34c/w) LTC3829fe: t j = t a + (p d ? 25c/w) note 4: the LTC3829 is tested in a feedback loop that servos v ith to a specifed voltage and measures the resultant v fb . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 8: guaranteed by design.
LTC3829 3829f typical p er f or m ance c harac t eris t ics phase shedding transition phase shedding transition prebiased output at 2v coincident tracking load step-up (0a to 75a, 75a/s) (nonlinear operation) load step-up (0a to 75a, 75a/s) (normal operation) v out 100mv/div ac-coupled v sw1 10v/div v sw2 10v/div v sw3 10v/div 2s/div 3829 g01 75mv v out 100mv/div ac-coupled v sw1 10v/div v sw2 10v/div v sw3 10v/div 2s/div 3829 g02 95mv run 2v/div v out1 = 3.3v v out2 = 1.5v 1v/div 2ms/div v in = 12v no load 3829 g06 v out1 v out2 v sw1 10v/div v sw2 10v/div v sw3 10v/div 2s/div v in = 12v 3829 g03 v sw1 10v/div v sw2 10v/div v sw3 10v/div 2s/div v in = 12v 3829 g04 v out 1v/div v fb 500mv/div tk/ss 500mv/div 2ms/div v in = 12v v out = 3.3v 3829 g05
LTC3829 3829f typical p er f or m ance c harac t eris t ics current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense voltage vs duty cycle maximum current sense voltage vs feedback voltage (current foldback) tk/ss pull-up current vs temperature quiescent current vs input voltage without extv cc intv cc line regulation input voltage (v) 0 2.00 intv cc voltage (v) 2.50 2.25 3.00 2.75 3.50 3.25 4.75 4.50 4.25 4.00 3.75 5.25 5 10 15 20 3829 g09 25 40 30 35 5.00 v ith (v) 0 ?40 v sense (mv) ?20 0 20 40 60 80 0.5 1 1.5 2 3829 g10 i lim = intv cc i lim = float i lim = gnd v sense common mode voltage (v) 0 0 current sense threshold (mv) 10 30 40 50 2 4 5 90 3829 g11 20 1 3 60 70 80 i lim = intv cc i lim = float i lim = gnd temperature (c) ?50 1.1 tk/ss current (a) 1.2 1.3 1.4 1.5 ?25 0 25 50 3829 g14 75 100 125 input voltage (v) 4 3.5 supply current (ma) 3.7 4.1 4.3 4.5 5.5 4.9 14 24 3829 g08 3.9 5.1 5.3 4.7 34 40 duty cycle (%) 0 maximum current sense voltage (mv) 60 80 100 80 3829 g12 40 20 50 70 90 30 10 0 2010 4030 60 70 90 50 100 i lim = intv cc i lim = float i lim = gnd feedback voltage (v) 0 maximum current sense voltage (mv) 60 80 100 0.4 0.5 3829 g13 40 20 50 70 90 30 10 0 0.1 0.2 0.3 0.6 i lim = intv cc i lim = float i lim = gnd shutdown (run) threshold vs temperature temperature (c) ?50 1.0 run pin voltage (v) 1.1 1.2 1.3 on off 1.4 ?25 0 25 50 3829 g15 75 100 125
LTC3829 3829f typical p er f or m ance c harac t eris t ics undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs input voltage shutdown current vs temperature quiescent current vs temperature without extv cc regulated feedback voltage vs temperature oscillator frequency vs temperature temperature (c) ?50 frequency (khz) 600 700 25 75 3829 g17 500 400 ?25 0 50 100 125 300 200 v freq 2.4v v freq = 1.2v v freq = 0v input voltage (v) 0 0 frequency (khz) 200 400 600 800 5 10 15 20 3829 g19 25 30 35 40 v freq 2.4v v freq = 1.2v v freq = 0v input voltage (v) 5 10 0 shutdown current (a) 20 50 15 25 30 3829 g20 10 40 30 20 35 40 temperature (c) ?50 40 50 70 25 75 3829 g21 30 20 ?25 0 50 100 125 10 0 60 shutdown current (a) temperature (c) ?50 quiescent current (ma) 4 5 6 25 75 3829 g22 3 2 ?25 0 50 100 125 1 0 temperataure (c) ?50 v fb (v) 0.600 0.602 0.604 25 75 3829 g16 0.598 0.596 ?25 0 50 100 125 0.594 0.592 temperature (c) ?50 2.5 uvlo threshold (v) 2.7 3.1 3.3 3.5 50 4.3 3829 g18 2.9 0 ?25 75 100 25 125 3.7 3.9 4.1 rising falling
LTC3829 3829f p in func t ions diffn (pin 1/pin 3): negative input of remote sensing differential amplifer. connect this to the remote load ground pin. diffp (pin 2/pin 4): positive input of remote sensing differential amplifer. connect this to the remote load positive terminal directly. run (pin 3/pin 5): run control input. a voltage above 1.22v on this pin turns on the ic. there is a 1.0a pull-up current for this pin. once the run pin rises above 1.22v, an additional 4.5a pull-up current is added to the pin. avp (pin 4/pin 6): active voltage positioning load slope programming pin. a resistor tied between this pin and the diffp pin sets the load slope. sense1 + , sense2 + , sense3 + (pins 5, 7, 11/pins 7, 9, 13): current sense comparator inputs. the (+) inputs to the current comparators are normally connected to dcr sensing networks or current sensing resistors. sense1 C , sense2 C , sense3 C (pins 6, 8, 12/pins 8, 10, 14): current sense comparator inputs. the (C) inputs to the current comparators are connected to the output. tk/ss (pin 9/pin 11): output voltage tracking and soft- start input. when one particular ic is confgured to be the master of two ics, a capacitor to ground at this pin sets the ramp rate for the master ics output voltage. when the ic is confgured to be the slave of two ics, the v fb voltage of the master ic is reproduced by a resistor divider and applied to this pin. an internal soft-start current of 1.25a is charging this pin. freq (pin 10/pin 12): there is a precision 10a current sourced out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. v fb (pin 13/pin 15): error amplifer feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider. i th (pin 14/pin 16): current control threshold and error amplifer compensation point. each associated channels current comparator tripping threshold increases with this i th control voltage. (uhf/fe) iset (pin 15/pin 17): stage shedding comparator and burst mode comparator programming pin. a resistor to ground programs the stage shedding comparator threshold or burst mode comparator threshold and its current limit depending on mode pin setting. i lim (pin 16/pin 18): current comparator sense voltage range pin. this pin is to be programmed to sgnd, float or intv cc to set the maximum current sense threshold to one of three different levels for each comparator. pgood (pin 17/pin 19): power good indicator output. open-drain logic out that is pulled to ground when the output exceeds 10% regulation window after the internal 100s power bad mask timer expires. pllin (pin 18/pin 20): external synchronization pin. a clock on the pin synchronizes the internal oscillator with the clock on this pin. extv cc (pin 23/pin 25): external power input to an internal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. do not exceed 6v on this pin and ensure v in > v extvcc at all times. intv cc (pin 24/pin 26): internal 5v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7f low esr tan- talum or ceramic capacitor. v in (pin 25/pin 27): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). bg1, bg2, bg3 (pins 30, 29, 22/pins 32, 31, 24): bottom gate driver outputs. these pins drive the gates of the bot- tom n-channel mosfets between pgnd and intv cc . sw1, sw2, sw3 (pins 31, 28, 21/pins 33, 30, 23): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . tg1, tg2, tg3 (pins 32, 27, 20/pins 34, 29, 22): top gate driver outputs. these are the outputs of foating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages.
LTC3829 0 3829f p in func t ions (uhf/fe) boost1, boost2, boost3 (pins 33, 26, 19/pins 35, 28, 21): boosted floating driver supplies. the (+) terminal of the bootstrap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . clkout (pin 34/pin 36): clock output pin. clkout is 60 out of phase relative to channel 1 in non-shedding mode. during stage shedding, clkout is 180 out of phase with channel 1. mode (pin 35/pin 37): forced continuous mode, burst mode or shed mode selection pin. connect this pin to sgnd to force ic in continuous mode of operation. con- nect to intv cc to enable shed mode operation. leave the pin foating to enable burst mode operation. ifast (pin 36/pin 38): programmable pin for nonlinear control trip threshold. a resistor to ground programs the tripping threshold for nonlinear control circuit. connect this pin to intv cc to disable this feature. see applications information section for details. itemp (pin 37/pin 1): input of the temperature sensing comparator. connect this pin to external ntc resistors placed near inductors. diffout (pin 38/pin 2): output of remote sensing differential amplifer. connect this pin to v fb through a resistive divider. sgnd/pgnd (exposed pad pin 39/exposed pad pin 39): combined signal and power ground pad. connect this pad closely to the sources of the bottom n-channel mosfets, the (C) terminal of c vcc and the (C) terminal of c in . all small-signal components and compensation components should also kelvin-connect to this pad.
LTC3829 3829f f unc t ional diagra m ? + ? ++ sleep iset intv cc 0.55v ? + ? + 0.5v ss ? + 1.22v run iset 1.25a v in ea i th r c c c1 c ss iset iset run tk/ss 0.6v ref s r q shed comp 5v reg ifast slope recovery active clamp osc mode/sync detect slope compensation uvlo 1 51k i thb 1.0a ifast clkout freq mode pllin itemp 0.6v bursten extv cc i lim ? + ? + i comp i rev f ? + 4.7v f 3k ? + ? + ov uv ? + ? ? + + ? + diffamp 0.54v v fb pgood pgnd c vcc c b m1 m2 v out l1 intv cc v in c out d b bg sense ? sense + sw tg boost intv cc diffout diffn 3829 bd sense1 + sense1 ? sense2 + sense2 ? sense3 + sense3 ? diffp sgnd avp 0.66v r1 r pre-avp 40k 40k 40k r avp 40k r2 switch logic and antishoot- through ov run on fcnt pll-sync tempsns + c in + v in
LTC3829 3829f o pera t ion main control loop the LTC3829 uses a constant frequency, current mode step-down architecture. during normal operation, each top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i cmp , resets each rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of the er- ror amplifer, ea. the remote sense amplifer (diffamp) produces a signal equal to the differential voltage sensed across the output capacitor and re-references it to the lo- cal ic ground reference. the v fb pin receives a portion of this feedback signal and compares it to the internal 0.6v reference. when the load current increases, it causes a slight decrease in the v fb pin voltage relative to the 0.6v reference, which in turn causes the i th voltage to increase until each inductors average current equals one-third of the new load current (assuming all three current sensing resistors are equal). after each top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, i rev , or the beginning of the next cycle. the main control loop is shut down by pulling the run pin low. releasing run allows an internal 1.0a current source to pull up the run pin. when the run pin reaches 1.22v, the main control loop is enabled and the ic is powered up. when the run pin is low, all functions are kept in a controlled state. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be derived from a high effciency external source such as a switching regulator output. each top mosfet driver is biased from the foating bootstrap capacitor, c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the dropout transition to ensure c b is recharged. shutdown and start-up (run and tk/ss pins) the LTC3829 can be shut down using the run pin. pulling the run pin below 1.22v shuts down the main control loop for the controller and most internal circuits, including the intv cc regulator. releasing the run pin allows an internal 1.0a current to pull up the pin and enable the controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the ab- solute maximum rating of 6v on this pin. the start-up of the controllers output voltage, v out , is controlled by the voltage on the tk/ss pin. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the LTC3829 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.25a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage, v out , rises smoothly from zero to its fnal value. alternatively, the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground (see the applications information section). when the run pin is pulled low to disable the controller, or when intv cc drops below its undervoltage lockout threshold of 3.3v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, all phases of the controller are disabled and the external mosfets are held off. (refer to functional diagram)
LTC3829 3829f light load current operation (burst mode operation, stage shedding or continuous conduction) the LTC3829 can be enabled to enter high effciency burst mode operation, stage shedding mode or forced continuous conduction mode. to select forced continuous operation, tie the mode pin to a dc voltage below 0.6v (e.g., sgnd). to select stage shedding mode of opera- tion, tie the mode pin to intv cc . to select burst mode operation, foat the mode pin. when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-sixth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. the peak current can be programmed through the iset pin. if the average inductor current is higher than the load current, the error amplifer, ea, will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v (can also be programmed by the iset pin), the internal sleep signal goes high (enabling sleep mode) and the external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the effciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode pin is connected to intv cc , the LTC3829 operates in stage shedding mode at light loads. the controller will turn off channels 2 and 3 and increase the current gain of the frst channel to ensure smooth transition. the threshold where the controller goes into stage shedding mode is when the i th voltage drops below 0.5v, but it can be programmed by iset pin. the inductor current is not allowed to reverse in this mode (discontinuous operation). at very light loads, the current comparator may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). this mode ex- hibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current effciency than forced continuous mode, but not nearly as high as burst mode operation. 2-chip operations (clkout pin) the LTC3829s three channels are 120 out of phase providing multiphase operation. this confguration can provide enough power for most high current applications. however, for even higher power applications, the LTC3829 can be confgured for polyphase ? and 2-chip operation. the LTC3829 features a clkout pin which enables two LTC3829s to operate out of phase. the clkout signal is 60 out of phase with respect to phase 1 of the controller. in stage shedding mode, however, the clkout signal is 180 out of phase with respect to phase 1 of the controller. frequency selection and phase-locked loop (freq and pllin pins) the selection of switching frequency is a trade-off between effciency and component size. low frequency opera- tion increases effciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. if the pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250khz to 770khz. there is a precision 10a current fowing out of the freq pin so that the user can program the controllers switching frequency with a single resistor to sgnd. a curve is provided later in the applications information section showing the relation- ship between the voltage on the freq pin and switching frequency. o pera t ion (refer to functional diagram)
LTC3829 3829f o pera t ion (refer to functional diagram) a phase-locked loop (pll) is available on the LTC3829 to synchronize the internal oscillator to an external clock source that is connected to the pllin pin. the pll loop flter network is integrated inside the LTC3829. the phase- locked loop is capable of locking any frequency within the range of 250khz to 770khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. the controller is operating in forced continuous mode when it is synchronized. sensing the output voltage with a differential amplifer the LTC3829 includes a low offset, unity-gain, high band- width differential amplifer for applications that require true remote sensing. sensing the load across the load capaci- tors directly greatly benefts regulation in high current, low voltage applications, where board interconnection losses can be a signifcant portion of the total error budget. the LTC3829 differential amplifer has a typical output slew rate of 2v/s. the amplifer is confgured for unity gain, meaning that the difference between diffp and diffn is translated to diffout, relative to sgnd. care should be taken to route the diffp and diffn pcb traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, the diffp and diffn traces should be shielded by a low impedance ground plane to maintain signal integrity. the maximum output voltage when using the differential amplifer is intv cc C 1.4v (typically 3.6v). above this output voltage the differential amplifer should not be used. power good (pgood pin) the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.6v reference voltage. the pgood pin is also pulled low when the run pin is below 1.22v or when the LTC3829 is in the soft-start or tracking phase. when the v fb pin voltage is within the 10% regulation window, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will fag power good immediately when the v fb pin is within the regulation window. however, there is an internal 100s power-bad mask when the v fb goes out of the window. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. undervoltage lockout the LTC3829 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.3v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 600mv of precision hysteresis. another way to detect an undervoltage condition is to moni- tor the v in supply. because the run pin has a precision turn-on reference of 1.22v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current fows out of the run pin once the run pin voltage passes 1.22v. the run comparator itself has about 80mv of hysteresis. one can program additional hysteresis for the run comparator by adjusting the val- ues of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.5v.
LTC3829 3829f a pplica t ions i n f or m a t ion the typical application on the frst page of this data sheet is a basic LTC3829 application circuit. the LTC3829 can be confgured to use either dcr (inductor resistance) sens- ing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power effcient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the se- lection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi- mum current limit of the controller. when i lim is either grounded, foated or tied to intv cc , the typical value for the maximum current sense threshold will be 30mv, 50mv or 75mv, respectively. which setting should be used? for the best current limit accuracy, use the 75mv setting. the 30mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. the 50mv setting is a good balance between the two. sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 5v. all sense + pins are high impedance inputs with small currents of less than 1a. the high impedance inputs to the current compara- tors allow accurate dcr sensing. all sense C pins and diffp should be connected to v out directly when dcr sensing is used. care must be taken not to foat these pins during normal operation. filter components mutual to the sense lines should be placed close to the LTC3829, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. c out to sense filter, next to the controller r sense 3829 f01 figure 1. sense lines placement with sense resistor low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the input common mode range of the current comparator is 0v to 5v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r v i i sense sense max max l = + ( ) ? 2 because of possible pcb noise in the current sensing loop, the ac current sensing ripple of ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 10mv ?v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mv for the ltc1628/ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. for todays highest current density solutions, however, the value of the sense resistor can be less than 1m and the
LTC3829 3829f a pplica t ions i n f or m a t ion peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 1mhz are becoming more common. under these conditions the voltage drop across the sense resistors parasitic inductance is no longer negligible. a typical sens- ing cir cuit using a discrete resistor is shown in figure 2a. in previous generations of controllers, a small rc flter placed near the ic was commonly used to reduce the ef- fects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical flter consists of two series 10 resistors connected to a parallel 1000pf capacitor, v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense ? sgnd LTC3829 v out 3829 f02a c f ? 2 ? r f esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f v in v in intv cc boost tg sw bg pgnd itemp r ntc *place c1 near sense + , sense ? pins **place r1 next to inductor inductor optional temp comp network dcrl sense + sense ? sgnd LTC3829 v out 3829 f02b r1** r2c1* r p r s r1 || r2 c1 = l dcr r sense(eq) = dcr r2 r1 + r2 (2a) using a resistor to sense current (2b) using the inductor dcr to sense current figure 2. two different methods of sensing current resulting in a time constant of 20ns. this same rc flter, with minor modifcations, can be used to extract the resis- tive component of the current sense signal in the presence of parasitic inductance. for example, figure 3 illustrates the voltage waveform across a 2m sense resistor with a 2010 footprint for the 1.2v/15a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current
LTC3829 3829f a pplica t ions i n f or m a t ion and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl v i t t t t esl step l on off on off = + ( ) ? ? (1) if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the resulting waveform looks resistive again, as shown in figure 4. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use equation 1 to determine the esl. however, do not overflter. keep the rc time constant, less than or equal to the inductor time constant to maintain a high enough ripple voltage of ?v sense . the above generally applies to high density/high current applications where i max > 10a and low values of inductors are used. for applications 500ns/div v sense 20mv/div 3829 f03 v esl(step) figure 3. voltage waveform measured directly across the sense resistor 500ns/div v sense 20mv/div 3829 f04 figure 4. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100 where i max < 10a, set r f to 10 and c f to 1000pf. this will provide a good starting point. the flter components need to be placed close to the ic. the positive and nega- tive sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible effciency at high load currents, the LTC3829 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of effciency compared to dcr sensing. if the external r1|| r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external flter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the induc- tor value calculation section, the target sense resistor value is: r v i i sense equiv sense max max l ( ) ( ) = + ? 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (25mv, 45mv or 68mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coeffcient of resistance, which is approximately 0.4%/c.
LTC3829 3829f a pplica t ions i n f or m a t ion a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r r dcr at t d sense equiv max l max = ( ) ( ) ( ) c1 is usually selected to be in the range of 0.047f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. t l(max) is the maximum inductor temperature. the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r r l dcr at c c 1 2 20 1 || ( ) ? = the sense resistor values are: r r r r r r r r d d d 1 1 2 2 1 1 = = ? || ; ? the LTC3829 also features a dcr temperature compen- sation circuit by using a ntc temperature sensor. see the inductor dcr sensing temperature compensation section for details. the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p r v v v r loss in max out out 1 1 = ? ( ) ( ) ? ensure that r1 has a power rating higher than this value. if high effciency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc- tion losses and provides higher effciency at heavy loads. peak effciency is about the same with either method. to maintain a good signal-to-noise ratio for the current sense signal, use a minimum ?v sense of 10mv for duty cycles less than 40%. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ? = ? v v v r c v v f sense in out out in osc 1 1? ? inductor dcr sensing temperature compensation and the itemp pin inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher effciency for applications of high output currents. however, the dcr of the inductor, which is the small amount of dc winding resistance of the copper, typically has a positive temperature coeffcient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. the LTC3829 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor to actively correct this error. the itemp pin, when left foating, is at a voltage around 5v and dcr temperature compensation is disabled. the itemp pin has a constant 10a precision current fowing out the pin. by connecting an ntc resistor from the itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according the following equation: v v v sensemax adj sense max itemp ( ) ( ) ? . ? . = 1 8 1 3 where: v sensemax(adj) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specifed in the electrical characteristics table. it is typically 75mv, 50mv or 30mv depending on the set- ting i lim pins. v itemp is the voltage of the itemp pin. the valid voltage range for dcr temperature compensa- tion on the itemp pin is between 0.5v to 0.2v, with 0.5v or above being no dcr temperature correction and 0.2v the maximum correction. however, if the duty cycle of the controller is less than 25%, the itemp range is extended from 0.5v to 0v.
LTC3829 3829f a pplica t ions i n f or m a t ion the ntc resistor has a negative temperature coeffcient, meaning its value decreases as temperature rises. the v itemp voltage, therefore, decreases as temperature in- creases and in turn, the v sensemax(adj) will increase to compensate the dcr temperature coeffcient. the ntc resistor, however, is nonlinear and the user can linear- ize its value by building a resistor network with regular resistors. consult the ntc manufacture data sheets for detailed information. another use for the itemp pins, in addition to ntc com- pensated dcr sensing, is adjusting v sense(max) to values between the nominal values of 30mv, 50mv and 75mv for a more precise current limit. this is done by applying a voltage less than 0.5v to the itemp pin. v sense(max) will be varied per the previous equation and the same duty cycle limitations will apply. the current limit can be adjusted using this method either with a sense resistor or dcr sensing. ntc compensated dcr sensing for dcr sensing applications where a more accurate current limit is required, a network consisting of an ntc thermistor placed from the itemp pin to ground will provide correction of the current limit over temperature. figure 2b shows this network. resistors r s and r p will linearize the impedance the itemp pin sees. to implement ntc compensated dcr sensing, design the dcr sense flter network per the same procedure mentioned in the previous selection, except calculate the divider components using the room temperature value of the dcr. for a single output rail operating from one phase: 1. set the itemp pin resistance to 50k at 25c. with 10a fowing out of the itemp pin, the voltage on the itemp pin will be 0.5v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the itemp pin resistance and the maximum inductor temperature which is typically 100c. use the equations: r v a v v i itemp c itemp c itemp c max 100 100 100 10 0 5 1 3 = . ? . ?? ( ) ? / ? ? ? . / dcr max r r r c c v sens 2 1 2 100 25 0 4 100 + ( ) ( ) ee max( ) calculate the values for r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c || r p r s = r itemp100c C r ntc100c || r p next, fnd the value of r p that satisfes both equations which will be the point where the curves intersect. once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet either in the form of graphs, tabulated data or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r r b t t o o = + + ? ? ? ? ? ? ? ? ? ? ? ? ? exp ? ? 1 273 1 273 where: r = resistance at temperature t, which is in degrees c r o = resistance at temperature t o , typically 25c b = b-constant of the thermistor. figure 5 shows a typical resistance curve for a 100k therm- istor and the itemp pin network over temperature. starting values for the ntc compensation network are listed below: ? ntc r o = 100k ? r s = 20k ? r p = 50k but, the fnal values should be calculated using the above equations and checked at 25c and 100c.
LTC3829 0 3829f a pplica t ions i n f or m a t ion after determining the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i v v dcr max at c max sensemax adj sense = ( ) ? / ( ) ? ? 3 25 1 ++ ( ) ( ) t c l max( ) ? ? . /25 0 4 100 where: v v v v a v sensemax adj sense max itemp ite ( ) ( ) ? . ? . ? = 1 8 1 3 mmp s p ntc a r r r = + ( ) 10 ? || use typical values for v sense(max) . subtracting constant a will provide a minimum value for v sense(max) . these values are summarized in table 1. table 1 i lim gnd float intv cc v sense(max) typ 30mv 50mv 75mv a 5mv 5mv 7mv the resulting current limit should be greater than or equal to i max for inductor temperatures between 25c and 100c. these are typical values for the ntc compensation network: ? ntc r o = 100k, b-constant = 3000 to 4000 ? r s 20k ? r p 50k generating the i max versus inductor temperature curve plot frst using the above values as a starting point and then adjusting the r s and r p values as necessary is another approach. figure 6 shows a typical curve of i max versus inductor temperature. the same thermistor network can be used to correct for temperatures less than 25c. but make sure v itemp is greater than 0.2v for duty cycles of 25% or more, oth- erwise temperature correction may not occur at elevated ambients. for the most accurate temperature detection, place the thermistors next to the inductors as shown in figure 7. take care to keep the itemp pin away from the switch nodes. inductor temperature (c) 10 resistance (k) 100 1000 10000 ?40 20 40 60 10080 120 1 ?20 0 3829 f05 thermistor resistance r o = 100k t o = 25c b = 4334 for 25c/100c r itmp r s = 20k r p = 43.2k 100k ntc figure 5. resistance versus temperature for the itemp pin network and the 100k ntc inductor temperature (c) ?40 i max (a) 15 20 25 20 60 120 3829 f06 10 5 0 ?20 0 40 80 100 corrected i max nominal i max uncorrected i max r s = 20k r p = 43.2k ntc thermistor: r o = 100k t o = 25c b = 4334 v out r ntc l1 sw1 l2 sw2 l3 sw3 3829 f07 figure 6. worst-case i max versus inductor temperature curve with and without ntc temperature compensation figure 7. thermistor location. place thermistor next to inductor(s) for accurate sensing of the inductor temperature, but keep the itemp pin away from the switch nodes and gate drive traces
LTC3829 3829f a pplica t ions i n f or m a t ion slope compensation and inductor peak current slope compensation provides stability in constant frequen- cy current mode architectures by preventing sub-harmonic oscillation at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak current for duty cycles greater than 40%. however, the LTC3829 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower effciency because of mosfet gate charge and transition losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the polyphase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing effciency. the inductor value has a direct effect on ripple current. the inductor ripple current, ?i l , per individual section n, decreases with higher inductance or frequency and increases with higher v in or v out : ? i v f l v v l out out in = ? ? ? ? ? ? ? ?1 where f is the individual output stage operating frequency. in a polyphase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 8 shows the net ripple current seen by the output capacitors for the different phase confgurations. the output ripple current is plotted for a fxed output voltage as the duty factor is varied between 10% and 90% on the x-axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations. the zero output ripple current is obtained when: v v k n where k n out in = = , ,..., ?1 2 1 figure 8. normalized peak output current vs duty factor [i rms = 0.3(i op-p )] duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3829 f08 di o(p-p) v o /fl 6-phase 4-phase 12-phase 3-phase 2-phase 1-phase
LTC3829 3829f a pplica t ions i n f or m a t ion power mosfet and schottky diode (optional) selection at least two external power mosfets must be selected for each of the three output sections: one n-channel mosfet for the top (main) switch and one or more n -channel mosfet(s) for the bottom (synchronous) switch. the number, type and on-resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on-resistance is normally less important for overall effciency than its input capaci- tance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on-resistance with signifcantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the voltage, v cc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specifcation for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge c urve included on most data sheets (figure 9). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the fat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is fat) is specifed for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying the ratio of the application v ds to the curve specifed v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specifed. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly specifed on mosfet data sheets. c rss and c os are specifed sometimes but defnitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switc out in = hh duty cycle v v v in out in = ? ? ? ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v i n r v main out in max ds on in = ? ? ? ? ? ? + ( ) + ( ) 2 1 ( ) 22 2 1 1 i r c v v v max dr miller cc th il ? ? ? ? ? ? ( )( ) + ? ? ( ) tth il sync in out in max f p v v v i n ( ) ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ?? ? + ( ) 2 1 r ds on( ) + ? v ds v in 3729 f09 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? figure 9. gate charge characteristic
LTC3829 3829f a pplica t ions i n f or m a t ion where n is the number of output stages, is the tem- perature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(il) is the data sheet speci- fed typical gate threshold voltage specifed in the power mosfet data sheet at the specifed drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20v, the high current effciency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher effciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes conduct during the dead time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in effciency. a 2a to 8a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. c in and c out selection in continuous mode, the source current of each top n-channel mosfet is a square wave of duty cycle v out / v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a close form equation can be found in application note 77. figure 10 shows the input capacitor ripple current for different phase confgurations with the output voltage fxed and input volt- age varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the product of phase number and output voltage, n(v out ), is approximately equal to the input voltage v in or: v v k n where k n out in = = , ,..., ?1 2 1 so the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. in the graph of figure 10, the local maximum input rms capacitor currents are reached when: v v k n where k n out in = = 2 1 1 2 ? , ,..., these worst-case conditions are commonly used for design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question.
LTC3829 3829f a pplica t ions i n f or m a t ion the figure 10 graph shows that the peak rms input current is reduced linearly, inversely proportional to the number n of stages used. it is important to note that the effciency loss is proportional to the input rms current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single-phase design. battery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a polyphase system. the required amount of input capaci- tance is further reduced by the factor n, due to the effective increase in the frequency of the current pulses. ceramic capacitors are becoming very popular for small designs but several cautions should be observed. x7r, x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. a secondary issue relates to the energy fowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low esr. the selection of c out is driven by the required effective series resistance (esr). typically once the esr requirement is satisfed the capacitance is adequate for fltering. the steady-state output ripple (?v out ) is determined by: ? ? v i esr nfc out ripple out + ? ? ? ? ? ? 1 8 where f = operating frequency of each stage, n is the number of output stages, c out = output capacitance and ?i l = ripple current in each inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. the output ripple will be less than 50mv at maximum v in with ?i l = 0.4i out(max) assuming: c out required esr < n ? r sense and c nf r out sense > ( ) ( ) 1 8 duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3829 f10 rms input ripple current dc load current 6-phase 4-phase 12-phase 3-phase 2-phase 1-phase figure 10. normalized input rms ripple current vs duty factor for one to six output stages
LTC3829 3829f a pplica t ions i n f or m a t ion the emergence of very low esr capacitors in small, surface mount packages makes very small physical implementa- tions possible. the ability to externally compensate the switching regulator loop using the i th pin allows a much wider selection of output capacitor types. the impedance characteristic of each capacitor type is signifcantly differ- ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance through-hole capacitors. the os-con semiconductor dielectric capacitors available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. ceramic capacitors from avx, taiyo yuden, murata and tokin offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount confgurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv, the kemet t510 series of surface mount tantalums or the panasonic sp series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo poscap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturers for other specifc recommendations. differential amplifer the LTC3829 has a true remote voltage sense capability. the sensing connections should be returned from the load, back to the differential amplifers inputs through a common, tightly coupled pair of pc traces. the differential amplifer rejects common mode signals capacitively or inductively radiated into the feedback pc traces as well as ground loop disturbances. the differential amplifer output signal is divided by a pair of resistors and is compared with the internal, precision 0.6v voltage reference by the error amplifer. active voltage positioning (avp) in an application, the avp scheme modifes the regu- lated output voltage depending its current loading. avp can improve overall transient response and save power consumption. the LTC3829 senses inductor current information through monitoring voltage drops on the sense resistor r sense or dcr sensing network of all three channels. the voltage drops are added together and applied as v pre-avp between the avp and diffp pins, which are connected through resistor r pre-avp . then v pre-avp is scaled through r avp and added to output voltage as the compensation for the load voltage drop. let: ? v = v sense1 + C v sense1 C ? v = v sense2 + C v sense2 C ? v = v sense3 + C v sense3 C then: ? ? v v r r diffp vout avp , ? = ? ? ? ? ? ? 3 pre-avp
LTC3829 3829f a pplica t ions i n f or m a t ion the fnal load slope is defned by the inductor current sense resistors and the two external resistors mentioned above. in summary, the load slope is: r r r v a sense avp ? / pre-avp ? ? ? ? ? ? the recommended value for r avp is 90 to 100. the maximum output voltage at avp is 2.5v. therefore, for output higher than 2.5v, avp function is not supported. the diffp pin, however, should always be connected to the output even when avp or diffamp functions are not used. programmable shed mode when the mode pin is tied to intv cc , the LTC3829 enters shed mode. it means that the second and third channel will stop switching when i th is below a certain programmed threshold. the threshold voltage on i th when LTC3829 goes into shed mode, is programmed according to the following formula: v shed = 0.5 + (5/3) ? (0.5 C v iset ) the valid range of v iset is between 0v to 0.5v and v iset is the voltage on the iset pin. there is a precision 7.5a fowing out of the iset pin. connecting a resistor to sgnd sets the v iset voltage. when left foating, v iset voltage will be at intv cc . the shed mode threshold voltage in this case will be 0.5v. there is a 50mv hysteresis for the shed mode threshold comparator. programmable burst mode operation when the mode pin is foating, the LTC3829 enters burst mode operation. this means that all channels will stop switching when i th is below a certain threshold. the burst mode clamp, which sets the current limit when bursting, can be programmed through v iset according to the following equation: v clamp = 0.7 + 0.62 (0.5 C v iset ) the valid range of v iset is between 0.3v to 0.5v and v iset is the voltage on the iset pin. there is a precision 7.5a fowing out of iset. connecting a resistor to sgnd sets the v iset voltage. when left foating, the v iset voltage will be at intv cc . the burst mode clamp voltage in this case will be 0.7v. there is a 50mv hysteresis for the burst mode comparator. nonlinear control loop the LTC3829 features a unique control loop that can speed up transient response dramatically. this feature is enabled and programmed through the ifast pin. when ifast is tied to intv cc , the nonlinear control loop is disabled. v ifast is the voltage that can be programmed on the ifast pin. there is a precision 10a fowing out of the iset pin. con- necting a resistor to sgnd sets the v ifast voltage. when v ifast is set below 0.5v, the difference of 0.5v and v ifast sets the threshold voltage that triggers nonlinear control.
LTC3829 3829f a pplica t ions i n f or m a t ion nonlinear control is only enabled when v fb is within the uv and ov window. it should be enabled only for forced continuous mode of operation. once nonlinear control is enabled, the top gate of all chan- nels will turn on if: v v v fb ref ifast = ? . ? ? . 0 5 5 1 2 the top gate of all channels will turn off if: v v v fb ref ifast = + 0 5 5 . ? where v ref is the reference voltage, normally at 0.6v, and v fb is the feedback voltage. soft-start and tracking the LTC3829 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when the controller is confgured to soft- start by itself, a capacitor should be connected to its tk/ss pin. the controller is in the shutdown state if its run pin voltage is below 1.22v and its tk/ss pin is actively pulled to ground in this shutdown state. if the run pin voltage is above 1.22v, the controller powers up. a soft-start cur- rent of 1.25a then starts to charge the tk/ss soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the control- ler but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defned to be the voltage range from 0v to 0.6v on the tk/ss pin. the total soft-start time can be calculated as: t c a softstart ss = 0 6 1 25 . ? . regardless of the mode selected by the mode pin, the controller always starts in discontinuous mode up to tk/ss = 0.5v. between tk/ss = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54v. the output ripple is minimized dur- ing the 40mv forced continuous mode window ensuring a clean pgood signal. when the channel is confgured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always fowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the LTC3829 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54v regardless of the setting on the mode pin. however, the LTC3829 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, the controller operates in discontinuous mode.
LTC3829 3829f a pplica t ions i n f or m a t ion the LTC3829 allows the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 11. in the following discussions, v out1 refers to the LTC3829s output as a master and v out2 refers to another supply output as a slave. to implement the coinci- dent tracking in figure 11a, connect an additional resistive divider to v out1 and connect its mid-point to the tk/ss pin of the slave controller. the ratio of this divider should be the same as that of the slave controllers feedback divider shown in figure 12a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 11b, the ratio of the v out2 divider should be exactly the same as the master controllers feedback divider shown in figure 12b . by selecting different resis- tors, the LTC3829 can achieve different modes of tracking including the two in figure 11. so which mode should be programmed? while either mode in figure 11 satisfes most practical applications, some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. under ratiometric tracking, when the master controllers output experiences dynamic excursion (under load transient, for example), the slave controller output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. figure 11. two different modes of output voltage tracking figure 12. setup and coincident and ratiometric tracking time (11a) coincident tracking v out1 v out2 output voltage 3829 f11a v out1 v out2 time 3829 f11b (11b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (12a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3829 f12 (12b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1
LTC3829 3829f a pplica t ions i n f or m a t ion intv cc (ldo) and extv cc the LTC3829 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the LTC3829s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5v when v in is greater than 5.5v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. each of these can supply a peak current of 100ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the LTC3829 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5v ldo or extv cc . when the voltage on the extv cc pin is less than 4.7v, the ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the effciency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics tables. for example, the LTC3829 intv cc current is limited to less than 42ma from a 38v supply in the uhf package and not using the extv cc supply: t j = 70c + (42ma)(38v)(34c/w) = 125c to prevent the maximum junction temperature from be- ing exceeded, the input supply current must be checked while operating in continuous conduction mode (mode = sgnd) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the intv cc ldo is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from one of switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start- up, short circuit). if more current is required through the extv cc than is specifed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . signifcant effciency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher effciency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (42ma)(5v)(34c/w) = 77c however, for low voltage outputs, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v ldo resulting in an effciency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest effciency. 3. ext v cc connected to an external supply. if a 5v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements.
LTC3829 0 3829f 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, effciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1 or 2.2 resistor as shown in figure 13 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the fnal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the effciency has improved. if there is no change in input current, then there is no change in effciency. setting output voltage the LTC3829 output voltage is set by an external feed- back resistive divider carefully placed across the output, as shown in figure 14. the regulated output voltage is determined by: v v r r out b a = + ? ? ? ? ? ? 0 6 1. ? to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. if diffamp is used, then the resistor, r b , should connect to the output of the diffamp, diffout. a pplica t ions i n f or m a t ion r vin 1 c in 3829 f13 5v c intvcc 4.7f + intv cc LTC3829 v in figure 13. setup for a 5v input figure 14. setting output voltage LTC3829 v fb v out r b c ff r a 3829 f14
LTC3829 3829f a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the LTC3829 includes current foldback to help limit load current when the output is shorted to ground. if the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the LTC3829 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short circuit ripple current is determined by the minimum on- time t on(min) of the LTC3829 (90ns), the input voltage and inductor value: ? i t v l l sc on min in ( ) ( ) ? = the resulting short-circuit current is: i v r i sc sense max sense l sc = ? ? ? ? ? ? 1 3 1 2 3 / ? ? ( ) ( ) ? phase-locked loop and frequency synchronization the LTC3829 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin pin. the turn-on of the second phases top mosfets is thus 120 out of phase with the external clock and so on. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal flter network. there is a precision 10a of current fowing out of freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the pllin pin. the internal switch between the freq pin and the integrated pll flter network is on, allowing the flter network to be pre-charged at the same voltage as of the freq pin. the relationship between the voltage on the freq pin and operating frequency is shown in figure 15 and specifed in the electrical characteristics table. if an external clock is detected on the pllin pin, the internal switch mentioned above turns off and isolates the infuence of the freq pin. note that the LTC3829 can only be synchronized to an external clock whose frequency is within range of the LTC3829s internal vco. this is guar- anteed to be between 250khz and 770khz. a simplifed block diagram is shown in figure 16. if the external clock frequency is greater than the inter- nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the flter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the flter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the flter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the flter capacitor c lp holds the voltage. typically, the external clock (on the pllin pin) input high threshold is 1.6v, while the input low threshold is 1v.
LTC3829 3829f a pplica t ions i n f or m a t ion minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC3829 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v v f on min out in ( ) < ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3829 is approximately 90ns, with reasonably good pcb layout, minimum 30% induc- tor current ripple and at least 10mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signifcant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. figure 15. relationship between oscillator frequency and voltage at the freq pin figure 16. phase-locked loop block diagram freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 38501 f15 2.5 0 100 300 400 500 900 800 700 200 600 digital phase/ frequency detector vco 2.4v 5v 10a r set 3829 f16 freq sync external oscillator pllin
LTC3829 3829f a pplica t ions i n f or m a t ion effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3829 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an output-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(effciency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor and current sense resistor. in continuous mode, the average output current fows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10m, r l = 10m, r sense = 5m, then the total resistance is 25m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. effciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. t ransition losses apply only to the topside mosfet(s), and become signifcant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: t ransition loss = (1.7) v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% effciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss.
LTC3829 3829f a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr) , where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-fltered closed-loop response test point. the dc step, rise time and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the fltered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 17. check the following in the pc layout:
LTC3829 3829f a pplica t ions i n f or m a t ion 1. keep the sgnd at one end of a printed circuit path thus preventing mosfet currents from traveling under the ic. the intv cc decoupling capacitor should be placed immediately adjacent to the ic between the intv cc pin and pgnd plane. a 1f ceramic capacitor of the x7r or x5r type is small enough to ft very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 5f to 10f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. the power ground returns to the sources of the bottom n-channel mosfets, anodes of the schottky diodes and (C) plates of c in , which should have as short lead lengths as possible. 2. does the ic diffp pin connect to the (+) plates of c out ? a 30pf to 300pf feedforward capacitor between the diffp and v fb pins should be placed as close as possible to the ic. 3. are the sense C and sense + printed circuit traces for each channel routed together with minimum pc trace spacing? the flter capacitors between sense + and sense C for each channel should be as close as possible to the pins of the ic. connect the sense C and sense + pins to the pads of the sense resistor as illustrated in figure 1. 4. do the (+) plates of c pwr connect to the drains of the topside mosfets as closely as possible? this capacitor provides the pulsed current to the mosfets. 5. keep the switching nodes, swn, boostn and tgn away from sensitive small-signal nodes (sense + , sense C , diffp, diffn, v fb ). ideally the swn, boostn and tgn printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv/dt traces from sensi- tive small-signal nodes with ground traces or ground planes. 6. u se a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible. 7. the 47pf to 330pf ceramic capacitor between the i th pin and signal ground should be placed as close as pos- sible to the ic. figure 17 illustrates all branch currents in a 3-phase switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic felds will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfets and schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. external opti-loop ? compensa- tion allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure.
LTC3829 3829f a pplica t ions i n f or m a t ion figure 17. branch current waveform + r in v in v out c in bold lines indicate high, switching currents. keep lines to a minimum length. + c out d3 d2 sw2 d1 l1 sw1 r sense1 l2 r sense2 l3 sw3 r sense3 3829 f17 r l
LTC3829 3829f typical a pplica t ion d2 cmdsh-3 clkout v fb i th iset diffn diffp diffout avp extv cc pgood itemp gnd tk/ss 34 13 14 15 1 2 38 4 23 17 37 39 clkout v osense ? v osense + extv cc pgood itemp sense1 + pllin ilim freq mode run ifast sense1 ? sense2 + c21 1000pf sense2 ? sense3 + c22 1000pf sense3 ? c23 1000pf LTC3829 diffout s3n 13.5k 40.2k 0 66.5 tg1 sw1 bg1 tg2 sw2 bg2 tg3 sw3 bg3 d1 cmdsh-3 100k 40.2k r26 100 r25 100 r24 100 r23 100 r22 100 r21 100 s3p s2n s2p s1n s1p 9 47pf diffout 20.0k 30.1k 100pf c ss 0.1f 0.1f 2.2 0.1f 1nf 5 6 7 8 11 12 18 16 10 35 36 25 3 pllin v in 24 intv cc 33 32 31 30 boost1 tg1 sw1 bg1 intv cc v in run mode 4.7f 16v 0.1f 26 27 28 29 boost2 tg2 sw2 bg2 d3 cmdsh-3 0.1f 19 20 21 22 boost3 tg3 sw3 bg3 q1 v in 10f 16v x5r l1 0.33h r sense1 0.001 r sense2 0.001 r sense3 0.001 q3 q4 100f 6.3v x5r v out 330f 2.5v sanyo s2 + q5 v in 10f 16v x5r s2p s2n l2 0.33h q1,q5,q9: rjk0305dpb q3,q4,q7,q8,q11,q12: rjk0330dpb q7 q8 100f 6.3v x5r v out 1.5v 60a gnd v out v osense ? v osense + 10 v out 3829 ta02 330f 2.5v sanyo s2 + q9 v in 10f 16v x5r l3 0.33h q11 q12 100f 6.3v x5r 330f 2.5v sanyo s2 + v in 180f 16v v in 7v to 14v gnd + 180f 16v + s3p s3n s1p s1n 10 1.5v, 60a converter using sense resistors, f sw = 400khz
LTC3829 3829f p ackage descrip t ion uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45o chamfer
LTC3829 3829f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev a) exposed pad variation aa 4.75 (.187) ref fe38 (aa) tssop 0608 rev a 0.09 ? 0.20 (.0035 ? .0079) 0o ? 8o 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
LTC3829 0 3829f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0410 ? printed in usa r ela t e d p ar t s part number description comments ltc3855 dual, multiphase, synchronous dc/dc step-down controller with differential remote sense phase-lockable fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12.5v ltc3860 dual, multiphase step-down dc/dc controller with differential remote sense and accurate current share works with drmos and power blocks for high current applications ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 24v, v out3 up to 13.5v ltc3850/ltc3850-1 ltc3850-2 dual 2-phase, high effciency synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v ltc3854 small footprint wide v in range synchronous step-down dc/dc controller, r sense or dcr current sensing fixed 400khz operating frequency, 4.5v v in 38v, 0.8v v out 5.25v, 2mm 3mm qfn-12 ltc3851/ltc3851-1 no r sense ? wide v in range synchronous step-down dc/dc controller, rs ense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3775 high frequency synchronous voltage mode step-down dc/dc controller fast transient response, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v in , msop-16e, 3mm 3mm qfn-16 ltc3878 no r sense constant on-time synchronous step-down dc/dc controller, no r sense required very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16 ltc3879 no r sense constant on-time synchronous step-down dc/dc controller, no r sense required very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v v out 0.9v in , msop-16e, 3mm 3mm qfn-16 typical a pplica t ion 1.2v/60a triple phase converter with active voltage positioning, f sw = 400khz + + intv cc extv cc i temp boost1 boost2 boost3 run i lim mode freq i th tk/ss sense1 + sense1 ? pgnd bg1 sw1 tg1 4.7f sw3 sw2 sw1 100k 75 100 0.1f 220pf 10k 20k 20k 22f 35v s3 v in 6v to 14v c out 330f 4v s6 v out 1.2v 60a sense2 + sense2 ? bg2 sw2 tg2 sense3 + sense3 ? bg3 clkout ifast sw3 tg3 sgnd diffout avp iset v fb diffn diffp pgood 0.3h v in v in 0.001 0.3h 0.001 0.3h 3829 ta03 0.001 v in LTC3829

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